FIT3159 Computer Architecture Applied Brief Semester 1, 2025 | MU

Cache Concepts and Organisation

Applied Brief:

Preparation is required for this Applied. Please do NOT plan to complete the Applied preparation during the Applied as this is not compatible with a ﬂipped Applied format.
The purpose of these ﬂipped Applieds is for students to get an opportunity to test their understanding of lecture material with a low cost in lost marks if they have not understood the material – rather than not understanding the material.
Students should produce written answers to the Applied questions prior to starting the Applied. For most questions the written answer will be worth 50% of the mark for that question.
Students will need to submit their answers before each Applied via Moodle [Turnitin] in PDF format by due date.
The answers will be reviewed in a question and answer format during the Applied. Each student will explain their answer.
Plan for a brief 60 second summary explanation of each question – focus on the most important and critical idea in the answer.
Marks will be awarded on the student’s ability to explain their submitted answers: concise, focused and accurate answers will earn full marks, answers with errors and lengthy explanations will lose marks. For most questions the verbal answer will be worth 50% of the mark for that question.
All questions are based on lecture slides, and lecture slides are in eﬀect the answer sheets for these Applieds.
Worked answers will not be posted after Applieds as most of the answers are already in the lecture slides and remaining will be thoroughly discussed in the class.

Question 1 (150 words max, 20%)

You are part of a team optimizing software for a wearable health device using a modern ARM-based processor.

A. Explain how cache memory improves execution efficiency in low-power, embedded processors.

B. Illustrate how temporal and spatial locality principles guide cache behavior when monitoring sensor data continuously.

C. Describe how a directly mapped cache would manage sensor data accesses in a constrained hardware environment.

D. Explain the role of the cache tag in ensuring correct memory access and data consistency.

Question 2 (150 words max, 20%)

You’re evaluating cache designs for a high-throughput system used in machine learning inference.

A. Explain how a set-associative cache balances performance and hardware complexity in such systems.

B. Describe the role of a Harvard (split) cache architecture in improving the parallelism of instruction and data processing.

C. Discuss how a multi-level cache hierarchy (L1, L2, L3) functions in a typical desktop processor (e.g., AMD Ryzen or Apple M-series) and how it reduces memory bottlenecks in data-intensive tasks.

Question 3 (150 words max, 20%)

You are debugging a performance bottleneck in a graphics processing pipeline running on a modern CPU.

A. Compare write-through and write-back caching strategies in terms of speed, data reliability, and consistency.

B. Describe how cache performance is estimated using hit and miss ratios, and explain how this measurement can guide optimization decisions for real-time workloads.

Question 4 (250 words max, 20%)

Choose any modern CPU model such as Apple M4, Intel Core i9, or AMD Ryzen 9 and answer the following:

A. Describe the cache hierarchy (e.g., presence of L1, L2, L3 caches, or unified/shared cache) in this CPU.

B. Specify the capacity of each cache level and how these sizes contribute to high-speed processing and reduced latency.

C. Identify the cache mapping techniques used at each level (e.g., set associative, fully associative) and explain their design significance.

D. State whether any of the caches follow a Harvard or unified architecture and justify its impact on parallel instruction/data handling.

E. Determine the write policy (write-through or write-back) used and discuss how it affects performance in modern workloads such as gaming or data science applications.

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Question 5 (150 words max, 20%)

You’re advising a system integrator comparing high-performance CPUs with fast SSDs for content creation workstations.

A. Contrast a CPU cache with an internal disk cache in terms of physical construction, speed, and role in system performance.

B. Discuss how the capacity of each cache type affects responsiveness, and outline key factors in choosing an optimal cache size, especially when balancing cost, speed, and workload type