design is constrained to two arithmetic units | My Assignment Tutor

, . The data flow graph (DFG) given 05w Q5 shows the operations and data EE 1 0203 dependencies of a digital system to be designed a, h, e, d and ease all 8-hit data inputs that are registered in the initial state and f is the output.

Figure Q5
11′ the design is constrained to two arithmetic units, where each arithmetic unit contains a multiplier and an adder. Construct the schedule of this DFG applying “as late as possible” (ALAP) scheduling. (b) Derive the corresponding RTL code for your design. (a) Obtain the FBD of the datapath unit of this digital system. (d) Obtain the FBD of the control unit showing all the control signals.
(8 marks) (6 marks) (( marks) (S marks)
(e) It is given that the propagation delay of thc components are as follows: the adder is 20 ns, multiplier is 120 ns and register is 10 ns. Calculate the maximum operating frequency of your design. (5 marks)

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