SECTION B Q4 A digital system is modelled by the RTL code in Listing Q4: Given a, b and c are 8-biti size and are external inputs. The registers are positive-edge triggered. By using the ALU with the functions given in Table Q4, answer the following questions. Note that in is I -bit and ne denotes in bitwise inverted.
Table Q4: ALU operation SO: ( ) / R1 b; S1: ( ) ( ) / R2 / R2 c; R1 * R2; fifo output function 00 X + Y ADD ( ) /R1 a; 01 X — Y SUB S2: (m) / R2 2R1; 10 X * Y Multiply (m*) / R2 R1 — R2; 11 Y PASS Y ( ) / done = 1; ( ) / goto SO;
Listing Q4: RTL code
(a) Derive the FBD of the datapath unit (DU) for the digital system in Q4.
(b) Write the Verilog code to model the datapath in Q4(a).
(c) Derive the FBD of the control unit (CU) showing the state registers, next state logics, output logics and all the control signals. Note: Group the control signals as a vector formatted as follows: sell, seI2, selY , Idl ,1c2, fl ,10, done. (7 marks)
(d) Given the values of a, b, c and 117 are 8, 2, 3 and 0 respectively, determine the value in register R2 when the signal done is activated. (5 marks) (e) If the multiply function is not available in the ALU, suggest an option to implement the operation of R2 ,– RI R2 in state S I if Y input is limited to 2, 4 and 8. (3 marks)